This application is based on and claims benefit of priority from the prior Japanese Patent Applications No. 2000-044299 filed Feb. 22, 2000 and No. 2000-53914 filed Feb. 29, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) having a matrix of signal and scan lines on a principal plane of a substrate, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and drivers integrally formed on the periphery of the principal plane of the substrate, to supply signal voltages.
2. Description of the Related Art
Recent flat displays, typically LCDs, are thin, light, and low power consumption, and therefore, are used for various appliances. Among LCDs, TFT-LCDs (thin-film transistor LCDs) are active matrix LCDs having pixel matrixes and TFTs serving as pixel switching elements. The TFT-LCDs provide clear images at high resolution that is comparable or superior to that of CRTs, and therefore, are used for applications that need high resolution.
Recent TFT-LCDs have drivers within them, to expand an effective display area on a transparent insulating substrate (hereinafter referred to as xe2x80x9carray substratexe2x80x9d) and reduce manufacturing costs. This type of TFT-LCD has a scan driver for supplying scan signals to pixel switching elements through scan lines, and a signal driver for supplying video signals to the pixel switching elements through signal lines. These drivers are integrated on an array substrate on which display pixels are formed. TFT-LCDs now being developed have sample-and-hold (S/H) drivers within them. This type of TFT-LCD employs a timing controller consisting of shift registers, etc., to control the sampling of video signals, signal line capacitors for holding video signals supplied through signal lines, and pixel capacitors (liquid crystal capacitors plus supplemental capacitors) into which the video signals from the signal line capacitors are written.
FIG. 1 shows a typical TFT-LCD that incorporates S/H drivers. The TFT-LCD 100 has a transmission-type LCD panel 110, a scan driver 120, and a signal driver 130. These components are integrated on an array substrate (not shown).
The display panel 110 has a matrix of signal lines S (representing signal lines S1, S2, and the like that are not shown) and scan lines G (representing scan lines G1, G2, and the like that are not shown). The signal lines S and the scan lines G intersect each other, and at each intersection, there is a TFT 113 serving as a pixel switching element. The TFT 113 has a source electrode connected to the signal line S and a drain electrode connected to a pixel electrode 114. The pixel electrode 114 faces a counter electrode 115 with a liquid crystal layer 116 interposing between them to provide liquid crystal capacitance Clc. The liquid crystal layer 116 is in parallel with a supplemental capacitor 117 that provides supplemental capacitance Cs. The liquid crystal capacitance Clc and supplemental capacitance Cs hold a video signal written through a signal line S for a given period. The counter electrode 115 receives a common potential Vcom from a counter electrode driver (not shown).
The scan driver 120 has shift registers (S/Rs) 121 and scan buffers 122 in pairs. In response to a vertical synchronizing signal IN2 and a vertical clock signal CLK2 from an external driver (not shown), the scan driver 120 successively provides the scan lines G with scan signals.
The signal driver 130 has shift registers (S/Rs) 131, analog switch buffers 132, video buses 133, and analog switches 134. The analog switches 134 are connected to the signal lines S, respectively. In response to a horizontal synchronizing signal IN1 and a horizontal clock signal CLK1 from the external driver, each shift register 131 provides synchronizing signals to control the analog switches 134 through the buffers 132 and analog switch control lines 135. As a result, video signals Video1 to VideoN from the external driver are sampled by the signal lines S at given timing.
In the following explanation, the video buses 133 are classified into as positive and negative video buses P1 to P12 and N1 to N12, and the analog switch control lines 135 are referred to as timing signal lines TS1 to TS4.
A peripheral area or frame area 140 is part of the surface area of the array substrate. The frame area 140 includes the scan driver 120 and signal driver 130 and does not include the display panel 110.
When manufacturing the TFT-LCD 100, the scan driver 120 and signal driver 130 are integrated on an array substrate, which may be an inexpensive glass substrate, through processes similar to those for the display panel 110. Therefore, the TFT-LCD 100 is manufacturable at lower costs than a TFT-LCD that employs a TAB technique to form a signal driver and a scan driver.
The TFT-LCD 100 has the scan driver 120 and signal driver 130 on the same array substrate where the display panel 110 is formed. This arrangement enlarges the frame area 140 compared with the TAB-type TFT-LCD. The present market prefers compact displays with large screens. It is required, therefore, to reduce the frame area 140 by reducing the circuit scale of TFTs that form the drivers in the frame area 140.
The size of an LCD is increasing, and the size of an array substrate is also increasing because each array substrate is required to provide as many panels as possible. A large array substrate involves shrinkage and expansion to increase process variations and deteriorate a positioning accuracy for an exposure unit to 1 xcexcm or more. It is very difficult, therefore, to further miniaturize the drivers. There is another problem as mentioned below.
FIG. 2 roughly shows the structure of the signal driver 130 of FIG. 1 formed on an array substrate. The scan driver 120 is not directly related to the present invention, and therefore, is omitted. Among the signal lines S, the signal line S1 is provided with an n-channel TFT (hereinafter referred to as xe2x80x9cn-TFTxe2x80x9d) serving as an analog switch SWna, and a p-channel TFT (hereinafter referred to as xe2x80x9cp-TFTxe2x80x9d) serving as an analog switch SWpa. Similarly, the signal line S2 is provided with an n-TFT serving as an analog switch SWnb and a p-TFT serving as an analog switch SWpb. The switches SWna and SWpa form an analog switch pair for the signal line S1, and the switches SWnb and SWpb form an analog switch pair for the signal line S2.
The n-TFT serving as the switch SWna and the p-TFT serving as the switch SWpa are formed side by side in parallel with the signal lines S1, S2, and the like. The drains (D) of these TFTs are connected to wires whose ends are commonly connected to the signal line S1. The source (S) of the n-TFT is connected to wiring that is connected to the video bus P2. The source of the p-TFT is connected to wiring that is connected to the video bus P1. The n- and p-TFTs serving as the switches SWnb and SWpb are similarly connected.
The gate (G) of the n-TFT serving as the switch SWna is connected to the timing signal line TS2, and the gate of the p-TFT serving as the switch SWpa is connected to the timing signal line TS3. The gate of the n-TFT serving as the switch SWnb is connected to the timing signal line TS4, and the gate of the p-TFT serving as the switch SWpb is connected to the timing signal line TS1.
FIGS. 3A and 3B are plan and sectional views showing the n-TFT serving as the switch SWna and the p-TFT serving as the switch SWpa of FIG. 2. FIG. 3A removes the top of the structure of FIG. 3B, i.e., some elements on the counter substrate side, to specifically show contact holes in one manufacturing step. There are a substrate 901, an active layer 911, a gate insulating film 906, an interlayer insulating film 908, a passivation film 910, gate electrodes 907, and source/drain electrodes 909. FIG. 3A shows the contact holes 921 and 922 for the source/drain electrodes 909. The contact holes 921 and 922 are linearly arranged in a gate width direction (a vertical direction in the figure) group by group each composed of four contact holes formed at regular intervals. The contact holes 921 and 922 have square shapes of substantially the same size.
As mentioned above, the LCD having signal and scan drivers integrated on an array substrate is capable of realizing high resolution. Accordingly, studies and developments for high resolution are energetically carried out. For example, 10.4-inch XGA (extended graphics arrays) panels and 8.4-inch SVGA (super video graphics arrays) panels have dot pitches of about 70 xcexcm. With these dot pitches, analog switch pairs each consisting of an n-TFT and a p-TFT can be formed side by side in parallel with the signal lines S as shown in FIG. 2. On the other hand, 4-inch VGA (video graphics arrays) panels have dot pitches of about 55 xcexcm, which do not allow the analog switch pairs to be formed side by side in parallel with the signal lines S. In this case, the n-TFTs and p-TFTs of the analog switch pairs must be shifted from each other by a gate width W as shown in FIG. 4. This arrangement must linearly form the drains of the n- and p-TFTs, to enlarge a frame area by at least the gate width W. This may degrade the product value of an LCD.
Shortening the length of each TFT and reducing the size of each contact require additional processes and process modifications, to deteriorate productivity and increase costs.
In this way, the conventional TFT-LCDs incorporating sample-and-hold drivers have the problem that the size of each TFT analog switch limits the resolution of the TFT-LCDs.
An object of the present invention is to provide an LCD capable of realizing high resolution without deteriorating productivity or increasing costs and the size of a frame area.
In order to accomplish the object, a first aspect of the present invention provides an LCD having a display panel, a signal driver for supplying video signals to signal lines, a scan driver for supplying scan signals to scan lines that intersect the signal lines, and an external driver for driving the signal and scan drivers. The display panel has an array substrate, a counter substrate, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate has the signal and scan lines, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and pixel electrodes connected to the pixel switching elements, respectively. The counter substrate has counter electrodes that face the pixel electrodes, respectively. The signal driver has positive video buses for transmitting positive video signals, negative video buses for transmitting negative video signals, p-TFT switches each connected to one of the positive video buses through wiring, and n-TFT switches each connected to one of the negative video buses through wiring. Among the p- and n-TFT switches, adjacent p- and n-TFT switches form a pair and are connected to one of the signal lines, and a p-TFT switch connected to a xe2x80x9c2Nxe2x88x921xe2x80x9dth (N being a natural number) one of the signal lines and a p-TFT switch connected to a xe2x80x9c2Nxe2x80x9dth one of the signal lines have source electrodes connected to a common contact hole that is connected to one of the positive video buses.
The first aspect may connect the source electrode of an n-TFT switch connected to a xe2x80x9c2Nxe2x80x9dth one of the signal lines and the source electrode of an n-TFT switch connected to a xe2x80x9c2N+1xe2x80x9dth one of the signal lines to a common contact hole that is connected to one of the negative video buses.
A second aspect of the present invention provides an LCD having a display panel, a signal driver for supplying video signals to signal lines, a scan driver for supplying scan signals to scan lines that intersect the signal lines, and an external driver for driving the signal and scan drivers. The display panel has an array substrate, a counter substrate, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate has the signal and scan lines, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and pixel electrodes connected to the pixel switching elements, respectively. The counter substrate has counter electrodes that face the pixel electrodes, respectively. The signal driver has positive video buses for transmitting positive video signals, negative video buses for transmitting negative video signals, p-TFT switches each connected to one of the positive video buses through wiring, and n-TFT switches each connected to one of the negative video buses through wiring. Among the p- and n-TFT switches, adjacent p- and n-TFT switches form a switch pair and are connected to one of the signal lines, and an n-TFT switch connected to a xe2x80x9c2Nxe2x88x921xe2x80x9dth (N being a natural number) one of the signal lines and an n-TFT switch connected to a xe2x80x9c2Nxe2x80x9dth one of the signal lines have source electrodes connected to a common contact hole that is connected to one of the negative video buses.
The second aspect may connect the source electrode of a p-TFT switch connected to a xe2x80x9c2Nxe2x80x9dth one of the signal lines and the source electrode of a p-TFT switch connected to a xe2x80x9c2N+1xe2x80x9dth one of the signal lines to a common contact hole that is connected to one of the positive video buses.
The first and second aspects share contact holes among the n- and p-TFT switches, to shorten the width of each switch pair. Compared with the prior art that separately forms source contact holes for n- and p-TFT switches, the first and second aspects can juxtapose the switch pairs to realize finer pixel pitches. Even at fine pixel pitches that the prior art must alternate p- and n-TFT switches, the present invention can form p- and n-TFT switches in parallel, to reduce circuit size. When applied to an LCD incorporating sample-and-hold drivers, the present invention realizes a simple structure to minimize a frame area of the LCD. Namely, the present invention provides a high-resolution LCD without enlarging a frame area where a signal driver is formed. The present invention forms pairs of p- and n-TFT switches on an array substrate through conventional manufacturing processes. Namely, the present invention needs no additional processes or process modifications for reducing TFT length and contact size, and therefore, involves no productivity loss or cost increase.
A third aspect of the present invention provides an LCD having a display panel, a signal driver for supplying video signals to signal lines, a scan driver for supplying scan signals to scan lines that intersect the signal lines, and an external driver for driving the signal and scan drivers. The display panel has an array substrate, a counter substrate, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate has the signal and scan lines, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and pixel electrodes connected to the pixel switching elements, respectively. The counter substrate has counter electrodes that face the pixel electrodes, respectively. The signal driver has positive video buses for transmitting positive video signals, negative video buses for transmitting negative video signals, p-TFT switches each connected to one of the positive video buses through wiring, and n-TFT switches each connected to one of the negative video buses through wiring. Adjacent p- and n-TFT switches among the p- and n-TFT switches form a switch pair and have drain electrodes that are adjacent to each other and are connected to one of the signal lines through a common contact hole extending over the drain electrodes.
The third aspect shares contact holes among the p- and n-TFT switches, to shorten the width of each switch pair. As a result, the third aspect can form the switch pairs side by side to realize fine pixel pitches and high resolution without enlarging a frame area of the LCD.
The third aspect may enlarge the common contact hole for the drain electrodes of each switch pair at least twice as large as each of contact holes for connecting the source electrodes of the switch pair to the video buses.
This realizes high resolution without enlarging an LCD frame area and secures electron mobility.
A fourth aspect of the present invention provides an LCD having a display panel, a signal driver for supplying video signals to signal lines, a scan driver for supplying scan signals to scan lines that intersect the signal lines, and an external driver for driving the signal and scan drivers. The display panel has an array substrate, a counter substrate, and a liquid crystal layer held between the array substrate and the counter substrate. The array substrate has the signal and scan lines, pixel switching elements formed at the intersections of the signal and scan lines, respectively, and pixel electrodes connected to the pixel switching elements, respectively. The counter substrate has counter electrodes that face the pixel electrodes, respectively. The signal driver has positive video buses for transmitting positive video signals, negative video buses for transmitting negative video signals, p-TFT switches each connected to one of the positive video buses through wiring, and n-TFT switches each connected to one of the negative video buses through wiring. Adjacent p- and n-TFT switches among the p- and n-TFT switches form a switch pair, the drain electrodes of each switch pair have toothed areas, respectively, and the toothed areas of each switch pair mesh with each other and are connected to one of the signal lines through contact holes each formed on a protruding tooth of the meshing toothed areas.
The fourth aspect forms a plurality of contact holes on each source/drain electrode of each TFT switch substantially along a straight line, to reduce the width of each switch pair. As a result, the fourth aspect can juxtapose switch pairs to narrow pixel pitches and realize high resolution without enlarging an LCD frame area. The fourth aspect provides the drain electrodes of adjacent TFT switches with toothed areas meshing with each other, to make a total drain width narrower than that of the third aspect, thereby further reducing dot pitches.
The fourth aspect may shape the contact holes on the meshing toothed areas of each switch pair into a single groove.
This secures electron mobility and simplifies device patterns to manufacture the LCD.